TKD Launches 625M Ultra-Low Jitter Differential Oscillator with 15fs Pure Heartbeat for 400G Single-Wave High-Speed Interconnection
Classification:
Release Time：2026-03-15
In the era of exponential explosion in AI computing power, data centers process massive volumes of information every second. As network architectures surge from 800G to 1.6T and even 3.2T, with single-channel PAM4 signal rates breaking through 112Gbps and accelerating towards 224Gbps, physical layer transmission is approaching its limits. At this point, every femtosecond (fs) of jitter in the clock source can become a fatal factor that erodes signal margin and leads to erroneous data transmission.
Addressing this industry pain point, TKD has released a 625MHz ultra-low jitter differential crystal oscillator. Leveraging independently developed lithographic High-Frequency Fundamental technology, the product achieves a true fundamental frequency output of 625MHz, with a phase jitter as low as an impressive 15fs (typical value) in the 12kHz~20MHz integration range. This product delivers a "one-step" pure reference clock for next-generation DSP and SerDes, eliminating spurs and phase noise elevation introduced by frequency multiplication of traditional Phase-Locked Loops (PLL) from the source.
Overview of Core Performance Indicators
Indicator | Parameter | Advantage |
Center Frequency | 625MHz | Supports customization of 156.25M/312.5M/625M |
Output | LVPECL / LVDS | Perfectly compatible with mainstream SerDes interfaces |
RMS Jitter | 15fs typ. | 12kHz~20MHz integration range,Outstanding level |
Frequency Stability | ±20ppm | High stability over temperature range |
Operation Temperature | -40℃ ~ +105℃ | Meets industrial-grade wide temperature and high-density heat dissipation requirements |
Supply Voltage | 3.3V / 2.5V | Flexibly adapts to different system architectures |
Package | 2016 / 2520 / 3225 | Miniaturized package, saving valuable internal space in optical modules |
Start-up Time | < 5ms | Fast response, supporting rapid cold start of AI clusters |
Targeting 224G: A Custom-Built "Clock Engine" for 400G Single-Wave
In the evolution of optical communication towards 1.6T/400G single-wave (224Gbps PAM4), traditional frequency-multiplied clock solutions of 156.25MHz or 312.5MHz have reached their physical limits.
Safeguarding the Stringent Jitter Budget：
In the 224G single-wave solution, the Unit Interval (UI) of the signal is extremely narrow, only about 8.9ps. The 15fs ultra-low jitter provided by TKD's 625MHz differential crystal oscillator accounts for only a tiny fraction of the UI cycle (approximately 0.17%). This preserves the critical jitter budget for signals after transmission through high-loss backplanes or complex photoelectric conversion, ensuring accurate sampling and data recovery by the DSP.
625M True Fundamental Frequency Direct Drive：
In the 1.6T (8x200G or 4x400G) architecture, the upward shift of the system reference clock frequency to 625MHz has become a mainstream trend. TKD's true fundamental frequency technology avoids instability factors caused by cross-clock domains and greatly reduces the risk of loss of lock in the Clock Data Recovery (CDR) inside the DSP.
15fs Ultra-Low Jitter: Translated into Tangible System-Level Benefits
The ultra-low jitter of 15fs and excellent phase noise performance (noise floor better than -160dBc/Hz at 10MHz offset) are not just numbers on a parameter sheet, but can be converted into significant system-level advantages:
Significantly Improving Pre-FEC Signal-to-Noise Ratio Margin
In high-speed PAM4 links, compared with traditional 50fs products, TKD's 15fs differential crystal oscillator can effectively improve the signal integrity of the Transmitter (Tx). The extremely pure clock significantly boosts the signal-to-noise ratio margin of the pre-Forward Error Correction (Pre-FEC) system, providing a wider and clearer decision window for the receiver DSP algorithm and ensuring the long-term operational robustness of the system.
Enhancing Adaptability to Complex Links and Environments
Ultra-low jitter effectively compensates for deterministic jitter in high-speed links, increasing the eye diagram opening angle at the Tx end of the optical module by approximately 15%. This performance gain greatly enhances the optical module's tolerance to high-loss PCB materials, demonstrating stronger connectivity capabilities in scenarios such as submarine optical cables, long-haul backbone networks and high-density plug-and-play applications.
Optimizing CDR Pressure and System Dynamic Power Consumption
The input of an extremely low-jitter clock means that there is no need to rely on extremely complex jitter cancellation algorithms inside the DSP/SerDes. This directly reduces the tap burden of equalizers (e.g., FFE/DFE) and the processing pressure of CDR circuits, thereby effectively optimizing the dynamic power consumption of the chipset and alleviating the severe heat dissipation challenges faced by 1.6T high-density optical modules.
From Crystal Oscillator to System: Professional-Grade Performance Comparison
System-Level Consideration | Traditional PLL Frequency Multiplication Solution | TKD Ture HFF solution | 1.6T/224G Evolution Gains |
Near-end phase noise | Spurs introduced by frequency multiplication | Clean, spur-free frequency spectrum | Reducing the risk of loss of lock in DSP CDR |
RMSJitter (12k-20M) | 50-80 fs | 15 fs (Typ.) | Meeting the stringent jitter budget of 224G single-wave |
Maximum Supported Single-Wave Rate | 112G PAM4 (facing bottlenecks) | 224G PAM4 (ideally adapted) | Supporting ultra-high-density switching of 1.6T/3.2T per port |
System Eye Diagram and Link | Tight judgement threshold | Increasing eye height by about 15% | Reducing the design difficulty of high-speed PCB materials (Loss) |
Empowering the Ultra-Fast Future: Typical System-Level Applications
- 1.6T/3.2T high-end optical modules: Providing 625M fundamental frequency reference for core DSP and Driver chips, eliminating spurs and supporting the extreme transmission of 224G PAM4 signals for single-wave.
- AI computing clusters and high-speed switching:Delivering ultra-low jitter reference clocks for high-speed private protocol interconnection inside supercomputers, NVLink and next-generation Ethernet switch chips.
- Coherent optical communication and high-order interconnection: The extremely low phase noise floor perfectly meets the requirements of high-order modulation (e.g., 16QAM/64QAM) in coherent optical communication, greatly optimizing the Error Vector Magnitude (EVM) performance.
- High-frequency radar and test & measurement: Ensuring extremely high phase consistency for beamforming of multi-channel phased array radars; meanwhile, guaranteeing that the ADC sampling accuracy of high-end oscilloscopes approaches the theoretical limit.
In today's era where optoelectronic interconnection is becoming increasingly extreme, through breakthroughs in underlying materials and lithographic processes, TKD is providing a rock-solid "domestically made pure core" for the global high-speed network infrastructure.
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