Taijing Technology Launches 625M Ultra-Low Jitter Differential Oscillator, 15fs ''Pure Heartbeat'' Direct Hit Single Wave 400g High-Speed Interconnect!

In the era where AI computing power is exploding exponentially, data centers are processing massive amounts of information every second. When the network architecture surges from 800G to 1.6T or even 3.2T, the single channel PAM4 signal rate breaks through 112Gbps and accelerates towards 224Gbps, and the transmission at the physical layer is approaching its limit. At this point, every femtosecond (fs) jitter of the clock source may become a fatal factor that devours signal margin and leads data transmission astray.

In response to the pain points in this industry, Taijing Technology has released a 625MHz ultra-low jitter differential crystal oscillator. This product adopts independently developed photolithography High Frequency Fundamental chip technology to achieve a true fundamental frequency output of 625MHz. In the integration range of 12kHz~20MHz, the phase jitter is as low as an astonishing 15fs (typical value). This product provides a "one-time molding" pure reference clock for the next generation DSP and SerDes, completely eliminating the spurious and phase noise caused by traditional phase-locked loop (PLL) multiplication from the source.

Overview of Core Performance Indicators

Sword Finger 224G: A clock engine tailored for single wave 400G

In the evolution of optical communication towards 1.6T/single wave 400G (224Gbps PAM4), traditional 156.25MHz or 312.5MHz frequency doubling clock schemes have reached their physical limits.

• Guarding the demanding Jitter Budget:

In the 224G single wave scheme, the unit interval (UI) of the signal is extremely narrow, only about 8.9ps. The 15fs ultra-low jitter provided by Taijing Technology's 625MHz differential crystal oscillator only accounts for a very small UI period (about 0.17%). This preserves a crucial jitter budget for signals that have undergone high loss backplane or complex optoelectronic conversion, ensuring that the DSP can accurately sample and recover data.

• 625M true fundamental frequency direct drive:

In the 1.6T (8x200G or 4x400G) architecture, the mainstream trend is to move the system reference clock frequency up to 625MHz. Taijing Technology's true fundamental frequency technology avoids the unstable factors caused by cross clock domains, greatly reducing the risk of CDR (clock data recovery) lock failure within DSP.

15fs ultra-low jitter: Transform into tangible system level dividends

The extremely low jitter of 15fs and excellent phase noise performance (with bottom noise better than -160dBc/Hz at 10MHz offset) are not only numbers on the parameter table, but also significant system level advantages:

• Significant improvement in Pre FEC signal-to-noise ratio margin

In high-speed PAM4 links, Taijing Technology's 15fs differential crystal oscillator can effectively improve the signal integrity of the transmitter (Tx) compared to traditional 50fs products. The extremely pure clock significantly improves the signal-to-noise ratio margin of the Pre FEC (pre error correction) system, providing a wider and clearer decision window for the DSP algorithm at the receiving end, ensuring the robustness of the system's long-term operation.

• Enhance the adaptability of complex links and environments

The ultra-low jitter effectively compensates for deterministic jitter in high-speed links, resulting in a 15% increase in the aperture angle of the Tx end eye diagram of the optical module. This performance gain greatly enhances the tolerance of optical modules to high loss PCB boards, demonstrating stronger connectivity when facing submarine optical cables, long-distance trunk networks, and high-density plug and play scenarios.

• Optimize CDR pressure and system dynamic power consumption

The extremely low jitter clock input means that there is no need to rely on DSP/SerDes to perform extremely complex jitter cancellation algorithms internally. This directly reduces the tap burden of equalizers (such as FFE/DFE) and the processing pressure of CDR circuits, effectively optimizing the dynamic power consumption of the chipset and alleviating the severe heat dissipation challenge faced by 1.6T high-density optical modules.

Professional level performance comparison from crystal oscillator to system

Empowering the Fast Future: Typical System Level Applications

• 1.6T/3.2T high-end optical module:

Provide 625M fundamental frequency reference for core DSP and Driver driver chips, eliminate spurious signals, and support the maximum transmission of single wave 224G PAM4 signals.

• AI computing cluster and high-speed exchange:

Provide ultra-low jitter reference clock for high-speed private protocol interconnection, NVLink, and next-generation Ethernet switching chips within supercomputers.

• Coherent optical communication and high-order interconnection:

The extremely low phase noise floor perfectly meets the requirements of high-order modulation (such as 16QAM/64QAM) in coherent optical communication, greatly optimizing EVM (error vector amplitude) performance.

• High frequency radar and testing measurement:

Ensure extremely high phase consistency in the beamforming of multi-channel phased array radar; At the same time, ensure that the sampling accuracy of high-end oscilloscope ADC approaches the theoretical limit.

In today's increasingly extreme optoelectronic interconnection, Taijing Technology is providing rock solid "domestically produced pure cores" for global high-speed network infrastructure through breakthroughs in underlying materials and photolithography processes.